The Invention herein described was made in the course of or under a contract or subcontract thereunder, with the Department of the Air Force.
1. Field of the Invention
The present invention relates to microelectronic devices with small vias therein and a method for forming small vias for circuit interconnections in fabricating microelectronic devices.
2. Description of the Prior Art and Background Considerations
In the fabrication of microelectronic devices, it has been recognized that significant increases in reliability and decreases in cost can be achieved through the use of full wafer LSI (large scale integration) involving multilevel interconnection technology.
In a wafer requiring small geometry, high density circuits, such as with CMOS and MOS devices, it is necessary to use smaller interconnections on the wafer by metallization routings or lines of 1 mil or less widths on each level of metallization with low resistance contact of the routings through small vias of such small sizes as 0.5 mil and smaller openings between levels.
To achieve such small vias, relatively thin dielectric layers at a thickness of a fraction of a micron must be employed; however, problems arise from such thin layers. Beyond a certain point, the dielectric thickness cannot be further reduced. For interlevel aluminum connection, for example, 0.5 .times. 0.5 mil vias were achieved on 0.3 micron thick RF-sputtered silicon dioxide, which is the most widely used dielectric material. This thickness was not considered sufficient for interlevel insulation for the basic reason that the pin hole density increases as the thickness of insulation decreases, thereby leading to a greater chance of interlevel short circuits. Furthermore, surface irregularities are less likely to be adequately covered and insulated when the dielectric thickness is too thin. Also, because the vias were etched through the RF-sputtered silicon dioxide, low resistance contact in the vias could not be achieved as a result of the fact that RF-sputtered silicon dioxide reacts with aluminum to form an insoluble residue which is extremely difficult to remove. Such residue hinders electrical contact and therefore increases contact resistance. Although such residue has been successfully avoided and eliminated by use of the mushroom-mask technique disclosed in U.S. Pat. No. 3,700,510, it has been found that, for best results, such a mushroom-mask technique preferably should not be used for via sizes of less than 3 mil diameter.
Another problem exists with reduced line widths, vis-a-vis small diameter vias and dielectric thickness. As an example, present systems can employ routing line widths of approximately 2 mil with a dielectric thickness of the order of 2 microns. A decrease in dielectric thickness by a factor of two would increase line capacitance by a factor of two, which increase in capacitance for a 2 inch line is presently believed to be unacceptable.
Accordingly, sufficient dielectric thickness must be maintained to keep line capacitance within reasonable values and to avoid pinholes. As stated above, an attempt to obtain small vias and low resistance contact therethrough is at variance with increasing dielectric thickness. As the thickness of the dielectric increases, the vias must accordingly increase in size; otherwise, it would not be possible to maintain low resistance contact through the vias between levels of metallization due to residues remaining after certain deposition techniques and due to the difficulty of depositing sufficient metal through such holes because of their combined depth and narrowness and/or because of the ragged edges of the vias, both of which militate against reliable, low resistance contact.
Stated succinctly, the viability of a multilevel technology depends to a large extent on the ability to obtain dependable, low contact resistance vias between relatively thick dielectric layers.